In order to support network processing, processors must be able to support a variety of operations such as instructions to interface with coprocessors. As the demand for faster processors rises, hardware acceleration of these operations becomes more and more important. Prior art processors have focused on increasing the speed of execution of individual instructions.
A RISC processor executes multiple instructions to access internal and external memory locations and interface with co-processors, e.g., the LOAD instruction and the STORE instruction. The LOAD instruction reads data from an external storage location or a port of a co-processor to a register of the RISC processor. The STORE instruction writes the content of a RISC processor register to an external storage location or to a port of a co-processor.
In prior art systems, a first instruction of the microcontroller requests data from an external memory address. The microcontroller receives the data. A second instruction performs a calculation on the data. A third instruction writes the modified data back to the external memory address. If multiple tasks and multiple microcontrollers are attempting to access and modify the same data, additional overhead is needed to prevent overlapping memory accesses from corrupting the data. For example, some microcontrollers add the overhead of semaphores to control access to shared data.
Thereby special handling is necessary. One implementation requires the use of semaphores to access shared data. A semaphore is a flag used by one task to inform other tasks that the data is being used by that task.
When dealing with high-speed data networks, there is a need for processors that allow for fast processing of data and communications with co-processors preferably within a single instruction cycle; such processors are not available now.